512-bit computing

In computer architecture, 512-bit integers, memory addresses, or other data units are those that are 512 bits (64 octets) wide. Also, 512-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. There are currently no mainstream general-purpose processors built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data.

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Computer architecture bit widths
Bit
1 4 8 12 16 18 24 26 30 31 32 36 45 48 60 64 128 256 512 bit slicing
Application
8 16 32 64
Binary floating-point precision
16 (×½) 24 32 (×1) 40 64 (×2) 80 128 (×4) 256 (×8)
Decimal floating-point precision
32 64 128
v t e

In computer architecture, 512-bit integers, memory addresses, or other data units are those that are 512 bits (64 octets) wide. Also, 512-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size.

There are currently no mainstream general-purpose processors built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data.

Representation

[edit]

A 512-bit register can store 2⁵¹² different values. The range of integer values that can be stored in 512 bits depends on the integer representation used.

The maximum value of a signed 512-bit integer is 2⁵¹¹ − 1, written in decimal as 6,703,903,964,971,298,549,787,012,499,102,923,063,739,682,910,296,196,688,861,780,721,860,882,015,036,773,488,400,937,149,083,451,713,845,015,929,093,243,025,426,876,941,405,973,284,973,216,824,503,042,047 (approximately 6.7039×10¹⁵³).

Hardware

[edit]

The Intel Xeon Phi has a vector processing unit with 512-bit vector registers, each one holding sixteen 32-bit elements or eight 64-bit elements, and one instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits long.^[1]

Some GPUs, such as the Advanced Micro Devices (AMD) Radeon HD 2900XT, the Nvidia GTX 280,^[2] GTX 285,^[3] Quadro FX 5800,^[4] and several Nvidia Tesla products, move data across a 512-bit memory bus. Then AMD Radeon R9 290, R9 290X and 295X2 followed.

AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed by Intel in July 2013, and released in 2016 with Knights Landing, and in 2017 on the HEDT and consumer server platform, with Skylake-X and Skylake-SP respectively.

Software

[edit]

Many hash functions, such as SHA-512 and SHA3-512, have a 512-bit output.

References

[edit]

^ "Intel Xeon Phi Coprocessor System Software Developers Guide" (PDF). Intel. March 2014. Archived (PDF) from the original on June 18, 2020. Retrieved April 30, 2019.
^ "GTX 280: Specifications". GeForce. Archived from the original on 2013-08-12. Retrieved 2013-08-13.
^ "GTX 285: Specifications". GeForce. Archived from the original on 2013-08-07. Retrieved 2013-08-13.
^ "Nvidia Quadro FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D". Nvidia.com. Archived from the original on 2019-06-11. Retrieved 2013-08-13.

Processor technologies

Models

Architecture

Instruction set
architectures

Types	Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes
Instruction sets	Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others

Execution

Instruction pipelining	Pipeline stall Operand forwarding Classic RISC pipeline
Hazards	Data dependency Structural Control False sharing
Out-of-order	Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue
Speculative	Branch prediction Memory dependence prediction

Parallelism

Level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed
Multithreading	Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative
Flynn's taxonomy	SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD

Processor
performance

Transistor count
Instructions per cycle (IPC)
- Cycles per instruction (CPI)
Instructions per second (IPS)
Floating-point operations per second (FLOPS)
Transactions per second (TPS)
Synaptic updates per second (SUPS)
Performance per watt (PPW)
Cache performance metrics
Computer performance by orders of magnitude

Types

By application	Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor
Systems on chip	System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC)
Hardware accelerators	Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor

Word size

Core count

Components

Functional units	Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder
Logic	Combinational Sequential Glue Logic gate Quantum Array
Registers	Processor register Status register Stack register Register file Memory buffer Memory address register Program counter
Control unit	Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter
Datapath	Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter
Circuitry	Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch

Power
management