Instruction unit

The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the control unit, which in turn is part of the CPU. In the simplest style of computer architecture, the instruction cycle is very rigid, and runs exactly as specified by the programmer. In the instruction fetch part of the cycle, the value of the instruction pointer (IP) register is the address of the next instruction to be fetched. This value is placed on the address bus and sent to the memory unit; the memory unit returns the instruction at that address, and it is latched into the instruction register (IR); and the value of the IP is incremented or over-written by a new value (in the case of a jump or branch instruction), ready for the next instruction cycle. This becomes a lot more complicated, though, once performance-enhancing features are added, such as instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.

Computer component

The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the control unit, which in turn is part of the CPU.^[1]

In the simplest style of computer architecture, the instruction cycle is very rigid, and runs exactly as specified by the programmer. In the instruction fetch part of the cycle, the value of the instruction pointer (IP) register is the address of the next instruction to be fetched. This value is placed on the address bus and sent to the memory unit; the memory unit returns the instruction at that address, and it is latched into the instruction register (IR); and the value of the IP is incremented or over-written by a new value (in the case of a jump or branch instruction), ready for the next instruction cycle.

This becomes a lot more complicated, though, once performance-enhancing features are added, such as instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.^[2]

See also

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• Branch prediction and the branch prediction buffer
  • Branch target predictor and the branch target buffer
  • Branch delay slot
• Instruction scheduling
  • Instruction selection
  • Data dependency or data hazard
  • Scoreboarding
• Very long instruction word (VLIW)
• Superscalar processor
• Opcode
• Analysis of Instruction parallelism, Instruction frequencies, Instruction mix
  • Instruction path length or Instruction count

References

[edit]

1. ^ Schneck, Paul B. (6 December 2012). Supercomputer Architecture - Paul B. Schneck - Google Książki. Springer. ISBN 9781461579571.
2. ^ John L. Hennessy and David A. Patterson (1990), Computer Architecture: a quantitative approach, Morgan Kaufmann Publishers, Palo Alto, USA, ISBN 1-55860-069-8

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