Random test generator
Random test generators (often abbreviated RTG or ISG for Instruction Stream Generator or Instruction Sequence Generator) are a type of computer software that is used in functional verification of microprocessors. Their primary use lies in providing input stimulus to a device under test. In a simulation/testbench verification environment, the simulator processes input created by the RTG and coverage monitors may be used to verify that the generator is properly testing the design. Random test generators range in scope from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems requiring extensive software development. Random test generators are most often created by the designing organizations.
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Random test generators (often abbreviated RTG or ISG[1] for Instruction Stream Generator or Instruction Sequence Generator[1]) are a type of computer software that is used in functional verification of microprocessors. Their primary use lies in providing input stimulus to a device under test.
In a simulation/testbench verification environment, the simulator processes input created by the RTG and coverage monitors may be used to verify that the generator is properly testing the design.[2]
Random test generators range in scope from simple scripts and parameterized macros that can be created in a matter of weeks to full featured systems requiring extensive software development. Random test generators are most often created by the designing organizations.
Table Based Generators
[edit]Table based test generators are the simplest RTGs available. Creation of such generators can be accomplished relatively quickly, and maintenance requirements are often low. These generators work by capturing knowledge of the design's instruction set architecture and storing it in a relational database for later use. Because of their simplistic nature, table based generators may be used by less skilled personnel to create interesting tests. There is a drawback to these generators however, as their implementation is generally restricted to simple architectures. Usage on more complex ISAs may result in an inability to reach corner cases or create complex scenarios. Table based generators may also generate invalid tests at times.
Static Generators
[edit]Static generators are similar to table based generators with the exception that the majority of the instruction, operand and data selection reside in complex procedural code. Static generators are capable of producing more random behavior than table based generators, but still have trouble hitting many corner-cases. In addition, the skill level required to create and maintain such a tool rises sharply once this level of sophistication is reached.
Dynamic Generators
[edit]Dynamic generators incorporate significant knowledge about the architecture being tested. They enhance the ability of less-skilled users to generate complex tests that can hit hard-to-reach corner cases without stumbling on subtle programming pitfalls. This added knowledge, flexibility and ease-of-use is reflected in a more complex generator, and consequently the cost of creating and maintaining the generator are greater than for table-based or static generators.
References
[edit]- ^ a b Introduction to FORCE-RISCV, OpenHW Group, February 21, 2023, retrieved February 25, 2023
- ^ "Random Test Generator - Bridging the gap | BCS". www.bcs.org. Retrieved February 25, 2023.