Posted write

A posted write is a computer bus write transaction that does not wait for a write completion response to indicate success or failure of the write transaction. For a posted write, the CPU assumes that the write cycle will complete with zero wait states, and so doesn't wait for the done. This speeds up writes considerably. For starters, it doesn't have to wait for the done response, but it also allows for better pipelining of the datapath without much performance penalty. A non-posted write requires that a bus transaction responds with a write completion response to indicate success or failure of the transaction, and is naturally much slower than a posted write since it requires a round trip delay similar to read bus transactions. In reference to memory bus accesses, a posted write is referred to as a posted memory write (PMW).

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A posted write is a computer bus write transaction that does not wait for a write completion response to indicate success or failure of the write transaction. For a posted write, the CPU assumes that the write cycle will complete with zero wait states, and so doesn't wait for the done. This speeds up writes considerably. For starters, it doesn't have to wait for the done response, but it also allows for better pipelining of the datapath without much performance penalty.

A non-posted write requires that a bus transaction responds with a write completion response to indicate success or failure of the transaction, and is naturally much slower than a posted write since it requires a round trip delay similar to read bus transactions.

In reference to memory bus accesses, a posted write is referred to as a posted memory write (PMW).

References

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PCI System Architecture, Don Anderson, Tom Shanley, MindShare, Inc - 1999

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Computer hardware buses and slots pinouts with brief descriptions

v t e Technical and de facto standards for wired computer buses
General	System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play Double data rate Quad data rate List of bus bandwidths
Standards	SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire
Storage	ST-506 ESDI SDI IPI SMD Floppy connector Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface)
Peripheral	Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt CAN bus
Audio	ADAT Lightpipe AES3 Intel HD Audio I²S MADI McASP S/PDIF TOSLINK
Portable	PC Card ExpressCard
Embedded	Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category

Posted write

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References

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