Cell software development

Software development for the Cell microprocessor involves a mixture of conventional development practices for the PowerPC-compatible PPU core, and novel software development challenges with regard to the functionally reduced SPU coprocessors.

An open source software-based strategy was adopted to accelerate the development of a Cell BE ecosystem and to provide an environment to develop Cell applications, including a GCC-based Cell compiler, binutils and a port of the Linux operating system.^[1]

Octopiler is IBM's prototype compiler to allow software developers to write code for Cell processors.^[2][3][4]

The VMX (Vector Multimedia Extensions) technology is conceptually similar to the vector model provided by the SPU processors, but there are a number of significant differences.

VMX to SPU Comparison^[1]
unfinished

feature	VMX	SPU
word size	32 bits	32 bits
number of registers	32	128
register width	128-bit quadword	128-bit quadword
integer formats	8, 16, 32	8, 16, 32, 64
saturation support	yes	no
byte ordering	big (default), little	big endian
floating point modes	Java, non-Java	single precision, IEEE double
Memory alignment	quadword only	quadword only

The VMX Java mode conforms to the Java Language Specification 1 subset of the default IEEE Standard, extended to include IEEE and C9X compliance where the Java standard falls silent. In a typical implementation, non-Java mode converts denormal values to zero but Java mode traps into an emulator when the processor encounters such a value.

The IBM PPE Vector/SIMD manual does not define operations for double-precision floating point, though IBM has published material implying certain double-precision performance numbers associated with the Cell PPE VMX technology.

Compilers for Cell^[who?] provide intrinsics to expose useful SPU instructions in C and C++. Instructions that differ only in the type of operand (such as a, ai, ah, ahi, fa, and dfa for addition) are typically represented by a single C/C++ intrinsic which selects the proper instruction based on the type of the operand.

A substantial amount of VMX (Altivec) code developed for IBM Power microprocessors, particularly under the PowerPC version of macOS, can potentially be adapted for use on the SPU. The feasibility of porting depends on the extent of VMX-specific features used—ranging from straightforward to impractical. However, key workloads typically map well to the SPU architecture.

In some cases, existing VMX code can be ported directly. If the VMX code is highly generic (makes few assumptions about the execution environment) the translation can be relatively straightforward. The two processors specify a different binary code format, so recompilation is required at a minimum. Even where instructions exist with the same behaviors, they do not have the same instruction names, so this must be mapped as well. IBM's development toolkit includes compiler intrinsics that automate much of this mapping.

In multiple cases, however, a directly equivalent instruction does not exist. The workaround might be obvious or it might not. For example, if saturation behavior is required on the SPU, it can be coded by adding additional SPU instructions to accomplish this (with some loss of efficiency). At the other extreme, if Java floating-point semantics are required, this is almost impossible to achieve on the SPU processor. To achieve the same computation on the SPU might require that an entirely different algorithm be written from scratch.

The most important conceptual similarity between VMX and the SPU architecture is supporting the same vectorization model. For this reason, most algorithms adapted to Altivec will usually adapt successfully to the SPU architecture as well.

Transferring data between the local stores of different SPUs can have a large performance cost. The local stores of individual SPUs can be exploited using a variety of strategies.

Applications with high locality, such as dense matrix computations, represent an ideal workload class for the local stores in Cell BE.^[5]

Streaming computations can be efficiently accommodated using software pipelining of memory block transfers using a multi-buffering strategy.^[1]

The software cache offers a solution for random accesses.^[6]

More sophisticated applications can use multiple strategies for different data types.^[7]

• The Cell Project at IBM Research
• Optimizing Compiler for a CELL Processor
• Using advanced compiler technology to exploit the performance of the Cell Broadband Engine architecture
• Compiler Technology for Scalable Architectures Archived 2009-01-29 at the Wayback Machine